ESD Solution &
Top Integration

 

 

What is ESD Engineering in VLSI Chips ?

ESD stress is a critical factor which determines the VLSI chip's reliability.
Thus, all the VLSI chips need to be equipped with robust and efficient ESD protection network.

The qualified ESD protection network do … protect chips against ESD stress , while it never interfere chip's normal operation.

ESD Fluxing Situation Normal Operation Situation

 

Factors to Determine Full Chip Level ESD Protection Performance

Traditional ESD engineering tends to focus on performance of ESD protection devices / cells only.
However, engineering focusing on ESD protection devices / cells only can not guarantee good ESD protection performance.

In fact, the full chip level ESD protection performance is determined by …,
(1) Chip's Basic Conditions (2) Quality of Unit ESD Solutions (3) Quality of Global Networking

 

Dilemma between Chip Size Reduction and ESD Protection Performance

Chip size determines price competitiveness.
Thus, designers have to make their chips as small as possible.

However, smaller chip size inevitably sacrifices the full chip level ESD protection performance.

Chip size determines price competitiveness

 

Correlation between Chip Level ESD Performance and System Level ESD Performance

During these times, system level ESD performance becomes more important, together with chip level ESD performance.
However, even chips qualified for chip level ESD test often face the system level ESD failure.

Reason for system level ESD failure and thumb rules for the corresponding amendment actions may be illustrated as follows;

 
Chip Level ESD Test ... Off State
 
Chip Level ESD Test ... Off State
 
  • Core path is 2-BJT path, while  path of the ESD protection network is 1-BJT path.
  • ESD stress is to be resolved via ESD devices, so that ESD fail does not occur.
     
System Level ESD Test ... On State    
     
Chip Level ESD Test ... Off State arrow Chip Level ESD Test ... Off State
     
  • Core path is 1-BJT path, which can compete with the path of ESD protection network.
  • Case ESD stress current rises in core region, it tends to flow core path and ESD fail can occur.
  
  • In order to cope with this problematic situation, effective and small ESD protection component has to be interwoven within the core region.

 

Why ESD Solution & Top Integration … !!

In order to guarantee good ESD protection performance, taking care of all of these issues …,
(1) Robust and effective ESD protection devices / cells are developed, first.
(2) These ESD protection components are properly adopted and well-arranged on the viewpoint of whole chip's geometry.
(3) ESD protection components on chip's peripheral region and ESD core compensation are well-balanced and well-interwoven.

In conclusion is …, ESD engineering together with art of top integration may be final solution.
This is the BauaBTech's way of ESD engineering!

ESD Protection Networking Based on Top Integration